Quentin Berthet's picture

Quentin Berthet

Professeur HES assistant

quentin.berthet@hesge.ch
+41 22 558 64 68
Bureau I309
Profil

Filière(s)

  • Ingénierie des technologies de l’information

Institut / Groupe de compétences

Adresse

HEPIA - Haute école du paysage, d'ingénierie et d'architecture
4 rue de la Prairie
1202 Genève

Publications
Development of a Central Trigger Processor board for the Advanced SiPM based camera of the CTA Large-Sized Telescopes
Pérez-Aguilera A., Molina-Delicado M., Dietrich T., Tejedor L.A., Barrio J.A., Upegui Posada A., Berthet Q., et al.
(2026)
Journal of Instrumentation 21, C01009, Topical Workshop on Electronics for Particle Physics (TWEPP2025), 06.-10.10.2025, Rethymno, Greece.
https://doi.org/10.1088/1748-0221/21/01/C01009
Hardware Architecture for Asynchronous Cellular Self-Organizing Maps
Berthet Q., Schmidt J., Upegui Posada A.
(2022)
Electronics 11, 215.
https://doi.org/10.3390/electronics11020215
A unified software/hardware scalable architecture for brain-inspired computing based on self-organizing neural models
Muliukov R., Rodriguez L., Miramond B., Khacef L., Schmidt J., Berthet Q., Upegui Posada A.
(2022)
DOI: https://doi.org/10.3389/fnins.2022.825879
Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application
Gantel L., Berthet Q., Amri Q., Karlov A., Upegui Posada A.
(2021)
https://doi.org/10.3390/electronics10172148
Trade Fairs
TDSCAN : Trigger Distributed Spatial Convolution Area Network (Poster)
Dietrich T., Burmistrov L., Heller M., Berthet Q., Upegui Posada A.
Fast Machine Learning for Science Conference, ETH Zurich,
https://indi.to/5ff3L
01.09.2025 to 05.09.2025
High Throughput FPGA Deployment of Distilled Deep Sets Networks for Jet Preselection in the High-Level Trigger (Poster)
Bezio L., Antel C., Berthet Q., Franchelucci S., Sfyria A.
Fast Machine Learning for Science Conference, ETH Zurich,
https://indi.to/fYC5K
01.09.2025 to 05.09.2025
Real-Time Data Processing for Cherenkov Telescopes Using FPGA-Accelerated 3D Convolution (Poster)
Dietrich T., Upegui Posada A., Berthet Q., Heller M., Burmistrov L.
AI Days @ HES-SO, Genève,
28.01.2025
High-Throughput FPGA Implementation of Deep Sets Neural Networks Using hls4ml (Poster)
Berthet Q., Antel C., Sfyrla A.
AI Days @ HES-SO, Genève,
28.01.2025
When existing architectures are not enough: Custom ML hardware architectures on FPGAs
Berthet Q.
AI Days @ HES-SO, Workshop "Edge AI - Tools, devices and methods", Genève,
27.01.2025
An area-efficient SPHINCS+ post-quantum signature coprocessor
Berthet Q., Upegui Posada A., Gantel L., Duc A., Traverso G.
DOI: 10.1109/IPDPSW52791.2021.00034
17.06.2021 to 21.06.2021